Saturday, February 2, 2013

ACCIDENT DETECTION AND VEHICLE TRACKING USING GPS,GSM AND MEMS


Hi all, 
Today i am sharing my major project with you,if you need ppt and materials you need to subscribe and join us.


INTRODUCTION

Now-a-days, it became very difficult to know that an accident has occurred and to locate the position where it has happened. It’s very difficult for the lives of victims until anyone noticed and informed it to the ambulance or to any hospital and if it occurs in remote areas there will be no hope to survive. To overcome these, GSM and GPS technologies are used. The GPS based vehicle accident identification module contains a vibrating sensor and a GPS modem connected to the microcontroller. When an accident occurs, the vibration sensor gives the signal to the microcontroller, which sends the information to the LCD display through GSM network. The vehicle is tracked for every five minutes using GPS and the position of the vehicle is also send to the mobile in terms of latitude and longitude which is processed by the pc.


Objective

The main aim of this project is to find the accident spot at any place and intimating the location to mobiles through the GSM and GPS networks. 

Hardware requirements

1. GSM MODULE 
2. GPS MODULE
3. ARM LPC2148
4. LCD DISPLAY
5. MEM SENSOR 
6. POWER SUPPLY 

Software requirements

1. Keil software 
2. Flash magic 


HARDWARE DESCRIPTION

ARM based LPC 2148 

The LPC2148 microcontrollers are based on a 32/16 bit ARM7TDMI-S CPU with real-time emulation and embedded trace support, that combines the microcontroller with embedded high speed flash memory ranging from 32 kB to 512 kB. A 128-bit wide memory interface and a unique accelerator architecture enable 32-bit code execution at the maximum clock rate. For critical code size applications, the alternative 16-bit Thumb mode reduces code by more than 30 % with minimal performance penalty. Due to their tiny size and low power consumption, LPC2141/2/4/6/8 are ideal for applications where miniaturization is a key requirement, such as access control and point-of-sale. A blend of serial communications interfaces ranging from a USB 2.0 Full Speed device, multiple UARTS, SPI, SSP to I2Cs and on-chip SRAM of 8 kB up to 40 kB, make these devices very well suited for communication gateways and protocol converters, soft modems, voice recognition and low end imaging, providing both large buffer size and high processing power. Various 32-bit timers, single or dual 10-bit ADC(s), 10-bit DAC, PWM channels and 45 fast GPIO lines with up to nine edge or level sensitive external interrupt pins make these microcontrollers particularly suitable for industrial control and medical systems.

Features of ARM

• 16/32-bit ARM7TDMI-S microcontroller in a tiny LQFP64 package.
• 8 to 40 kB of on-chip static RAM and 32 to 512 kB of on-chip flash program memory .128 bit wide interface/accelerator enables high speed 60 MHz operation.
• In-System/In-Application Programming (ISP/IAP) via on-chip boot-loader software. Single flash sector or full chip erase in 400 ms and programming of 256 bytes in 1 ms.
• Embedded ICE RT and Embedded Trace interfaces offer real-time debugging with the on-chip Real Monitor software and high speed tracing of instruction execution.
• USB 2.0 Full Speed compliant Device Controller with 2 kB of endpoint RAM. In addition, the LPC2146/8 provides 8 kB of on-chip RAM accessible to USB by DMA.
• One or two (LPC2141/2 vs. LPC2144/6/8) 10-bit A/D converters provide a total of 6/14 analog inputs, with conversion times as low as 2.44 μs per channel.
• Single 10-bit D/A converter provide variable analog output.
• Two 32-bit timers/external event counters (with four capture and four compare channels each), PWM unit (six outputs) and watchdog.
• Low power real-time clock with independent power and dedicated 32 kHz clock input.
• Multiple serial interfaces including two UARTs (16C550), two Fast I2C-bus (400 kbit/s), SPI and SSP with buffering and variable data length capabilities.

Applications of ARM Processor

• Industrial control
• Medical systems
• Access control 
• Point-of-sale 
• Communication gateway 
• Embedded soft modem
• General purpose applications

Architectural overview of ARM Processor

The LPC2148 consists of an ARM7TDMI-S CPU with emulation support, the ARM7 Local Bus for interface to on-chip memory controllers, the AMBA Advanced High-performance Bus (AHB) for interface to the interrupt controller, and the VLSI Peripheral Bus (VPB, a compatible superset of ARM’s AMBA Advanced Peripheral Bus) for connection to on-chip peripheral functions. The LPC2148 configures the ARM7TDMI-S processor in little-endian byte order. AHB peripherals are allocated a 2 megabyte range of addresses at the very top of the 4 gigabyte ARM memory space. Each AHB peripheral is allocated a 16 kB address space within the AHB address space. LPC2148 peripheral functions (other than the interrupt controller) are connected to the VPB bus. The AHB to VPB bridge interfaces the VPB bus to the AHB bus. VPB peripherals are also allocated a 2 megabyte range of addresses, beginning at the 3.5 gigabyte address point. Each VPB peripheral is allocated a 16 kB address space within the VPB address space. The connection of on-chip peripherals to device pins is controlled by a Pin Connect Block (see chapter "Pin Connect Block" on page 75). This must be configured by software to fit specific application requirements for the use of peripheral functions and pins.

ARM7TDMI-S Processor

The ARM7TDMI-S is general purpose 32-bit microprocessor, which offers high performance and very low power consumption. The ARM architecture is based on Reduced Instruction Set Computer (RISC) principles, and the instruction set and related decode mechanism are much simpler than those of micro programmed Complex Instruction Set Computers. This simplicity results in a high instruction throughput and impressive real-time interrupt response from a small and cost-effective processor core.
Pipeline techniques are employed so that all parts of the processing and memory systems can operate continuously. Typically, while one instruction is being executed, its successor is being decoded, and a third instruction is being fetched from memory. The ARM7TDMI-S processor also employs a unique architectural strategy known as THUMB, which makes it ideally suited to high-volume applications with memory restrictions, or applications where code density is an issue. The key idea behind THUMB is that of a super-reduced instruction set. Essentially, the ARM7TDMI-S processor has two instruction sets:

The standard 32-bit ARM instruction set.
A 16-bit THUMB instruction set.
The THUMB set’s 16-bit instruction length allows it to approach twice the density of     standard ARM code while retaining most of the ARM’s performance advantage over a traditional 16-bit processor using 16-bit registers. This is possible because THUMB code operates on the same 32-bit register set as ARM code.
THUMB code is able to provide up to 65% of the code size of ARM, and 160% of the performance of an equivalent ARM processor connected to a 16-bit memory system. The ARM7TDMI-S processor is described in detail in the ARM7TDMI-S Datasheet that can be found on official ARM website.



11 comments:

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i hve subscribed bt hw cn i download?

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I require ppt and all material asap thank you

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